Modern digital integrated circuits such as central processing units (CPUs) are typically capable of operating with several different clock frequencies. Assume that a CPU can reduce its clock frequency while still meeting the processing requirements of an application that is running on the CPU. As is well known, a reduction in the clock frequency of the CPU proportionally reduces the CPU power consumption. With a lower clock frequency less power is consumed because there are fewer signal level changes within a given time period.
As is also well known, the power consumption of a digital circuit is quadratrically proportional to the operating voltage. Therefore, decreasing the voltage level of the operating voltage (i.e., the supply voltage) and reducing the clock frequency can provide significant power savings in a digital circuit.
Dynamic Voltage Scaling (DVS) is a power management technique in which pre-determined voltage values (within a voltage table) are used for each requested operating clock frequency of a CPU. The voltage levels that are defined in the voltage table must be carefully selected in order to adequately cover all process and temperature corners so that the CPU will function correctly at each clock frequency.
Adaptive Voltage Scaling (AVS) is a power management technique in which the supply voltage of a digital integrated circuit is adjusted automatically. The supply voltage is adjusted (using closed loop feedback) to a minimum level that is required for the proper operation of the integrated circuit at a given clock frequency.
The major difference between Dynamic Voltage Scaling (DVS) and Adaptive Voltage Scaling (AVS) is that the Adaptive Voltage Scaling (AVS) includes automatic variation of the process and temperature in order to balance the supply voltage and system delay (digital cell delay) that is due to closed loop feedback. This means that the supply voltage in the AVS system is automatically reduced at lower temperatures and for faster silicon. As the supply voltage is reduced, the power consumption is also reduced.
FIG. 1 illustrates a block diagram of an embodiment of an exemplary prior art Adaptive Voltage Scaling (AVS) System 100. AVS System 100 comprises a System-on-a-Chip (SoC) unit 110 and an Adaptive Voltage Scaling (AVS) Regulator 120. System-on-a-Chip (SoC) unit 110 comprises a Clock Management Unit (CMU) 130, a Variable Voltage Domain CPU System 140, a Hardware Performance Monitor (HPM) 150, and an Advanced Power Controller (APC) 160. The Hardware Performance Monitor (HPM) 150 is located within the Variable Voltage Domain CPU System 140.
The Clock Management Unit (CMU) 130 receives a system clock signal from a system clock unit (not shown). The Clock Management Unit (CMU) 130 provides clock frequencies for the central processing unit (CPU) (not separately shown) in the Variable Voltage Domain CPU System 140. The Clock Management Unit (CMU) 130 also provides clock frequencies for the Hardware Performance Monitor (HPM) 150. The clock frequencies that are provided to the Hardware Performance Monitor (HPM) 150 are represented by the designation “HPM CLOCK”.
The Hardware Performance Monitor (HPM) 150 tracks gate delays in the current operational conditions. The Hardware Performance Monitor (HPM) 150 is in the Variable Voltage Domain CPU System 140. The Hardware Performance Monitor (HPM) outputs a performance code to the Advanced Power Controller (APC) 160. The performance code indicates the propagation delay of digital gate cells. The Advanced Power Controller (APC) 160 processes the delay data and requests appropriate changes to the supply voltage.
The Advanced Power Controller (APC) 160 is coupled to and communicates with the Adaptive Voltage Scaling (AVS) regulator 120. In one embodiment the coupling between the Advanced Power Controller (APC) 160 and the Adaptive Voltage Scaling (AVS) regulator 120 is a PowerWise™ interface (PWI). The mark PowerWise™ is a trademark of the National Semiconductor Corporation. The Advanced Power Controller (APC) 160 sends a request to the Adaptive Voltage Scaling (AVS) regulator 120 to change the supply voltage. The Adaptive Voltage (AVS) regulator 120 provides the requested supply voltage level to the SoC 110. The adjustable supply voltage from the Adaptive Voltage Scaling (AVS) regulator 120 is designated VAVS in FIG. 1.
The operating system of a modern central processing unit (CPU) may support a real time scheduling of performance levels. Each performance level has associated with it a specific value of operating clock frequency. The operating system is capable of selecting an operating clock frequency for which the CPU performance is minimized on a real time basis and for which the deadlines of a particular application are still met. For example, while an MPEG4 movie encoding application is running, a performance scheduling algorithm of the operating system may predict and change the performance level of the CPU in ten millisecond (10 ms) intervals.
The Hardware Performance Monitor (HPM) 150 tracks gate delays in the current operational conditions. The Hardware Performance Monitor (HPM) 150 outputs a performance code to the Advanced Power Controller 160. The performance code indicates the propagation delay of digital gate cells. In particular, Hardware Performance Monitor (HPM) 150 sends the performance code to the Advanced Power Controller 160. The Advanced Power Controller 160 then subtracts the performance code from a standard Reference Calibration Code (RCC) to obtain an error signal.
The error signal is referred to as “Slack Time”. The Slack Time error signal comprises a digital error signal in a two's complement number format. If the Slack Time is positive an increase in voltage is required. If the Slack Time is negative a decrease in voltage is required. The Slack Time error signal is provided to a Compensation Unit (not shown) within the Advanced Power Controller 160. Based on the value of the Slack Time error signal, the Compensation Unit sends a signal to AVS Regulator 120 to cause AVS Regulator 120 to adjust the value of the adjustable output voltage (VAVS) of AVS Regulator 120.
The central processing unit (CPU) of an adaptive voltage scaling system may change its performance levels over relatively short intervals of time, possibly in millisecond intervals of time. Therefore, a relatively fast rising supply voltage transient may be required for some applications.
The closed loop control system of an adaptive voltage scaling system requires the use of a loop filter. The loop filter sets the bandwidth and the transient response speed of the closed loop. The loop filter also tends to reduce the difference between the output of the Hardware Performance Monitor (HPM) 150 and a desired Reference Calibration Code (RCC) value.
The loop filter of an adaptive voltage scaling system is typically implemented using an integrator circuit. The use of an integrator circuit is always required if steady-state error must be completely cancelled from the output of the system. However, using an integrator circuit for the loop filter has a significant drawback. The integrator circuit will always slow down the original transient response of the adaptive voltage scaling regulator in a closed loop mode. This means that the slew rate of the adjustable supply voltage signal is limited.
Whenever the central processing unit (CPU) requests a higher operating frequency, the supply voltage must be increased by the closed loop before the higher clock frequency can be enabled for the CPU. If the slew rate of the supply voltage signal is limited, the speed with which a new, higher operating frequency can be enabled is limited as well.
Therefore, there is a need in the art for a system and method for rapidly increasing a rising slew rate of an adjustable power supply signal in an adaptive voltage scaling system.